1. Field of the Invention
The present invention relates to a semiconductor process, and more particularly, to a method of forming a contact hole and a method of fabricating a semiconductor device.
2. Description of the Related Art
The technology of the present Ultra-Large Semiconductor Integrated (ULSI) circuit has developed under 0.18-μm. In other words, the metal and semiconductive contacts are to be smaller and smaller. Therefore, how to overcome misalignment of contact resulting from the small line widths is an important issue in the semiconductor industry.
In order to overcome the smaller line width and prevent misalignment of the contacts, self-aligned contact (SAC) design has been widely adopted in fabricating semiconductor device processes. The SAC technique can also be used to electrically connect doped regions in the substrate and the conductive lines over the substrate.
FIGS. 1A–1D are schematic cross sectional views showing progression of a prior art SAC process.
Referring to FIG. 1A, a substrate 100 is provided. A source region 108 is formed in the substrate 100. A trench-type gate structure 102 is partially formed in the substrate 100. A silicon oxide dielectric layer 104 and a polysilicon conductive layer 106 are sequentially formed over the gate structure 102 and the surface of the substrate 100. A silicon nitride spacer material layer 110 is then formed over the conductive layer 106.
Referring to FIG. 1B, an anisotropic etch process is performed to remove a portion of the spacer material layer 110 so as to form spacers 110a on the sidewalls of the conductive layer 106 of the gate structure 102. By using the spacers 110a as a mask, the exposed conductive layer 106 is removed to form openings 112 in the conductive layer 106 between every two neighboring gate structures 102. Drain regions 114 are then formed in the substrate 100 at the bottoms of the openings 112.
Referring to FIG. 1C, a silicon nitride dielectric layer 116 is then formed on the sidewalls of the conductive layers 106a of the openings 112. A dielectric layer 118 is formed over the substrate 100.
Referring to FIG. 1D, portions of the dielectric layer 118 and dielectric layer 104 at the bottoms of the openings 112 are removed to form a plurality of self-aligned contact holes 120, and the dielectric layers 104a and 118a. Conductive plugs 122 are formed in the self-aligned contact holes 120.
Because of the low etching selectivity, about 10, of the polysilicon conductive layer 106 to the silicon nitride spacer material 110, the silicon nitride spacer material 110 adjacent to the openings 112 (area 124 in FIG. 1B) is gradually removed during the step of forming the openings 112. As a result, the spacer material layer 110 is thinner than the other areas. In the subsequent step of forming the self-aligned contact holes 120, the spacers 110a at the area 124 cannot effectively protect the conductive layers 106a thereunder and exposes the conductive layers 106a as shown in FIG. 1D. A subsequent process of forming conductive plugs will short the conductive plugs and the exposed conductive layers 106a. Accordingly, device performances are affected.